This paper describes a new approach to the implementation of the central signal processing functions of a parallel formant speech synthesiser using a bit-serial VLSI structure developed using the FIRST silicon compiler. The VLSI primitives have been arranged in a tightly looped structure with a high degree of computational concurrency to optimise the design for speed. This leads to a synthesis device which has a processing bandwidth far in excess of that required for real-time speech production. This excess may either be used for wide band speech synthesis or as the central signal processing element in a multiple channel formant speech synthesis device.